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data sheet idt8T79S838-08NLGI revision a january 29, 2014 1 ?2014 integrated device technology, inc. 1-to-8 differential to universal output ? fanout buffer idt8t79s838-08i general description the idt8t79s838-08i is a high performance, 1-to-8, differential input to universal output fanout buffer. the device is designed for signal fanout of high-frequency clock signals in applications requiring output frequencies generated simultaneously. the idt8t79s838-08i is optimized for 3.3v and 2.5v supply voltages and a temperature range of -40c to 85c. the device is packaged in a space-saving 32 lead vfqfn package. features four banks of two output pairs individual output type control, lvds or lvpecl, via ? serial interface individual outputs remain enabled while serial loading new ? device configurations one differential pclk, npclk input pclk, npclk input pair can accept the following differential input levels: lvpecl, lvds levels maximum input frequency: 1.5ghz lvcmos control inputs individual output enable/disable control via serial interface 2.375v to 3.465v supply voltage operation -40c to 85c ambient operating temperature lead-free (rohs 6) packaging block diagram qa0 nqa0 qa1 nqa1 qb0 nqb0 qb1 nqb1 qc0 nqc0 qc1 nqc1 qd0 nqd0 qd1 nqd1 pclk npclk oe le miso sclk sdata vcc vee vee vee vee vee pwr_sel vee pullup / pulldown pulldownpulldown pulldown pulldown pulldown pulldown vee output type and output enable logic idt8t79s838-08i 32 lead vfqfn 5mm x 5mm x 0.925mm pad size 3.15mm x 3.15mm nl package top view 25 26 27 28 29 30 31 1 2 3 4 5 6 7 16 15 14 13 12 11 10 24 23 22 21 20 19 18 v cc v ee nqa1 qa1 nqa0 qa0 v cc sdata 32 8 9 17 v cc v ee qd0 nqd0 qd1 nqd1 v cc pwr_sel s c l k m i s o n c p c l k n p c l k o e v c c l e q b o n q b 0 q b 1 n q b 1 q c 0 n q c 0 q c 1 n q c 1 pin assignment
idt8T79S838-08NLGI revision a january 29, 2014 2 ?2014 integrated device technology, inc. idt8t79s838-08i data sheet 1-to-8 differential to universal output fanout buffer pin description and pin characteristic tables table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see ?table 2. pin characteristics? for typical values. table 2. pin characteristics number name type description 1 sclk input pulldown serial control port mode data input. lvcmos/lvttl interface levels. 2 miso output serial control port mode data output. lvcmos/lvttl interface levels. 3 nc unused no connect. 4 pclk input pulldown non-inverting differential clock input. 5n p c l k i n p u t pullup / pulldown inverting differential clock input. v cc / 2 by default when left floating. 6 oe input pulldown default output disable. lvcmos/lvttl interface levels. ? see ?table 3b. oe truth table? . 7, 10, 16, 25, 31 v cc power power supply voltage pin. 8 le input pulldown serial control port mode enable. latc hes data when the pin gets a high level. outputs remain enabled when le is lo w. lvcmos/lvttl interface levels. 9 pwr_sel input pulldown power supply selection. see ?table 3a. pwr_sel truth table? . 11, 12 nqd1, qd1 output differen tial bank d output pair. 13, 14 nqd0, qd0 output differen tial bank d output pair. 15, 26 v ee power negative power supply pins. 17, 18 nqc1, qc1 output diff erential bank c output pair. l vpecl or lvds interface levels. 19, 20 nqc0, qc0 output diff erential bank c output pair. l vpecl or lvds interface levels. 21, 22 nqb1, qb1 output differenti al bank b output pair. lvpecl or lvds interface levels. 23, 24 nqb0, qb0 output differenti al bank b output pair. lvpecl or lvds interface levels. 27, 28 nqa1, qa1 output differenti al bank a output pair. lvpecl or lvds interface levels. 29, 30 nqa0, qa0 output differenti al bank a output pair. lvpecl or lvds interface levels. 32 sdata input pulldown serial control port mode data input. lvcmos/lvt tl interface levels. symbol parameter test conditio ns minimum typical maximum units c in input capacitance 2 pf r pulldown input pulldown resistor 51 k ? r pullup input pullup resistor 51 k ? r out output impedance miso v cc = 3.3v 125 ? v cc = 2.5v 125 ?
idt8T79S838-08NLGI revision a january 29, 2014 3 ?2014 integrated device technology, inc. idt8t79s838-08i data sheet 1-to-8 differential to universal output fanout buffer function tables table 3a. pwr_sel truth table table 3b. oe truth table output type control and start-up status two output types are available: lvds and lvpecl. the part features four modes of output type control: ? eight lvds outputs ? eight lvpecl outputs ? two lvds (qax) + six lvpecl (qbx, qcx, qdx) ? two lvpecl (qax) + six lvds (qbx, qcx, qdx) at startup, the outputs are in st atic low/high lvds mode until the part has been configured. disabled outputs are in static low/high mode. a global hardware output enable (oe pin #6) enables or disables all outputs at once. the global hardware oe has priority over a serial interface configuration. table 3c. output type control pwr_sel function l (connect to v ee ) 2.5v power supply h (connect to v cc ) 3.3v power supply oe function l (default) all outputs disabled (low/high static mode), rega rdless of individual oe registers set by serial interface. h outputs enabled according to individual oe registers set by serial interface (see ?table 3e. configuration table? ). control bits output configuration d2 d1 low low 8 lvds outputs high high 8 lvpecl outputs high low 2 lvds (qax) + 6 lvpecl (qbx, qcx, qdx) outputs low high 2 lvpecl (qax) + 6 lvds (qbx, qcx, qdx) outputs
idt8T79S838-08NLGI revision a january 29, 2014 4 ?2014 integrated device technology, inc. idt8t79s838-08i data sheet 1-to-8 differential to universal output fanout buffer serial interface configuration of the idt8t79s838i-08 is achieved by writing 10 configuration bits over serial interface. all 10 bits have to be written in sequence. after writing the 10 configuration bits, the le pin must remain at high level for outputs to toggle. ' ' ' ' ' 0,62 ' ' ' ' ' 6&/. 6'$7$ /( w 6/ w 6 w + w +( w +, w /2 w '(/$< w 6+ figure 1. serial interface timing diagram for write and read access table 3d. timing ac characteristics note: electrical parameters are guaranteed over the specified ambient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. symbol parameter test conditions minimum typical maximum units t s data to clock setup time 10 ns t h data to clock hold time 10 ns t he clock to le hold time 10 ns t hi clock high duration 25 ns t lo clock low duration 25 ns t sl le to clock setup time 10 ns t sh le to sclk setup time 10 ns t delay clock to miso delay time 10 ns
idt8T79S838-08NLGI revision a january 29, 2014 5 ?2014 integrated device technology, inc. idt8t79s838-08i data sheet 1-to-8 differential to universal output fanout buffer table 3e. configuration table bit name function truth table d10 oed1 output enable qd1 low: disabled high: enabled d9 oed0 output enable qd0 d8 oec1 output enable qc1 d7 oec0 output enable qc0 d6 oeb1 output enable qb1 d5 oeb0 output enable qb0 d4 oea1 output enable qa1 d3 oea0 output enable qa0 d2 ot1 banks qb, qc, qd output type low: lvds high: lvpecl d1 ot0 bank qa output type
idt8T79S838-08NLGI revision a january 29, 2014 6 ?2014 integrated device technology, inc. idt8t79s838-08i data sheet 1-to-8 differential to universal output fanout buffer absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operati on of product at these conditions or an y conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, v o (lvcmos) -0.5v to v cc + 0.5v outputs, i o (lvpecl) ? continuous current ? surge current ? outputs, i o (lvds) ? continuos current ? surge current ?50ma ? 100ma? 10ma ? 15ma package thermal impedance, ? ja 48.9 ? c/w (0 mps) storage temperature, t stg -65 ? c to 150 ? c dc electrical characteristics table 4a. power supply dc characteristics, v cc = 3.3v 5%, v ee = 0v, t a = -40c to 85c table 4b. power supply dc characteristics, v cc = 2.5v 5%, v ee = 0v, t a = -40c to 85c item rating symbol parameter test conditio ns minimum typical maximum units v cc power supply voltage 3.135 3.3 3.465 v i ee power supply current d[10:1] = high, lvpecl 120 135 ma i cc power supply current d[10:3] = high; d[2:1] = low, lvds 215 235 ma symbol parameter test conditio ns minimum typical maximum units v cc power supply voltage 2.375 2.5 2.625 v i ee power supply current d[10:1] = high, lvpecl 114 125 ma i cc power supply current d[10:3] = high; d[2:1] = low, lvds 210 230 ma
idt8T79S838-08NLGI revision a january 29, 2014 7 ?2014 integrated device technology, inc. idt8t79s838-08i data sheet 1-to-8 differential to universal output fanout buffer table 4c. lvcmos/lvttl dc characteristics, v cc = 3.3v 5% or 2.5v 5%, v ee = 0v, t a = -40c to 85c table 4d. differential input dc characteristics, v cc = 3.3v 5% or 2.5v 5%, v ee = 0v, t a = -40c to 85c note 1: common mode input voltage is defined at the cross point. table 4e. lvpecl dc characteristics, v cc = 3.3v 5% or 2.5v 5%, v ee = 0v, t a = -40c to 85c note 1: outputs terminated with 50 ? to v cc ? 2v. table 4f. lvds dc characteristics, v cc = 3.3v 5% or 2.5v 5%, v ee = 0v, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units v ih input high voltage v cc = 3.3v 2.2 v cc + 0.3 v v cc = 2.5v 1.7 v cc + 0.3 v v il input low voltage v cc = 3.3v -0.3 0.8 v v cc = 2.5v -0.3 0.7 v i ih input high current oe, le, pwr_sel, ? sclk, sdata v cc = v in = 3.465v or 2.625v 150 a i il input low current oe, le, pwr_sel, ? sclk, sdata v cc = 3.465v or 2.625v, v in = 0v -10 a v oh output high voltage miso v cc = 3.465v, i oh = -1ma 2.6 v v cc = 2.625v, i oh = -1ma 1.8 v v ol output low voltage miso v cc = 3.465v or 2.625v, i ol = 1ma 0.5 v symbol parameter test conditio ns minimum typical maximum units i ih input high current pclk, npclk v cc = v in = 3.465v or 2.625v 150 a i il input low current pclk v cc = 3.465v or 2.625v, v in = 0v -10 a npclk v cc = 3.465v or 2.625v, v in = 0v -150 a v pp peak-to-peak voltage 0.15 1.3 v v cmr common mode input voltage; note 1 1.0 v cc ? 0.5 v symbol parameter test conditions minimum typical maximum units v oh output high voltage; note 1 v cc ? 1.3 v cc ? 0.75 v v ol output low voltage; note 1 v cc ? 2.0 v cc ? 1.6 v v swing peak-to-peak output voltage swing 0.6 1.0 v symbol parameter test conditio ns minimum typical maximum units v od differential output voltage 247 454 mv ? v od v od magnitude change 50 mv v os offset voltage 1.125 1.45 v ? v os v os magnitude change 50 mv
idt8T79S838-08NLGI revision a january 29, 2014 8 ?2014 integrated device technology, inc. idt8t79s838-08i data sheet 1-to-8 differential to universal output fanout buffer ac electrical characteristics table 5. ac characteristics, v cc = 3.3v 5% or 2.5v 5%, v ee = 0v, t a = -40c to 85c note: electrical parameters are guaranteed over the specified ambient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. ? note 1: this parameter is defined in accordance with jedec standard 65. ? note 2: defined as skew between outputs at the same supply volt age and with equal load conditions. measured at the differential crosspoints. ? note 3: defined as skew within a bank of outputs at the same voltage and with equal load conditions. ? note 4: defined as skew between outputs on different devices oper ating at the same supply voltage, same frequency, same tempera ture and with equal load conditions. using the same type of inputs on each device, the outputs are measured at the differential crosspoi nts. ? note 5: measured from the differential input cr osspoint to the different ial output crosspoint. symbol parameter test conditions minimum typical maximum units f in input frequency pclk, npclk 1.5 ghz f out output frequency qx, nqx 1.5 ghz t pd propagation delay; note 5 lvpecl 200 650 ps lvds 200 650 ps t sk (o) output skew; ? note 1, 2 lvpecl 80 ps lvds 80 ps t sk (b) bank skew; ? note 1, 3 lvpecl 55 ps lvds 55 ps t sk (pp) part-to-part skew; ? note 1, 4 lvpecl 450 ps lvds 450 ps t r / t f output rise/fall time lvpecl 20% to 80% 50 300 ps lvds 20% to 80% 50 300 ps odc output duty cycle lvpecl 40 60 % lvds 40 60 %
idt8T79S838-08NLGI revision a january 29, 2014 9 ?2014 integrated device technology, inc. idt8t79s838-08i data sheet 1-to-8 differential to universal output fanout buffer parameter measurement information 3.3v lvpecl output load test circuit 3.3v lvds output load test circuit differential input levels 2.5v lvpecl output load test circuit 2.5v lvds output load test circuit propagation delay scope qx nqx v ee v cc 2v -1.3v 0.165v v cc v cc v ee npclk pclk scope qx nqx v ee -0.5v 0.125v v cc 2v v cc t pd npclk pclk nqx[0:1] qx[0:1]
idt8T79S838-08NLGI revision a january 29, 2014 10 ?2014 integrated device technology, inc. idt8t79s838-08i data sheet 1-to-8 differential to universal output fanout buffer parameter measurement in formation, continued output skew part-to-part skew lvpecl output rise/fall time bank skew lvds output rise/fall time output duty cycle/pulse width/period nqx qx nqy qy t sk(pp) part 1 part 2 qx nqx qy nqy nqx[0:1] qx[0:1] t sk(b) qxx nqxx qxy nqxy where x = a single output bank 20% 80% 80% 20% t r t f v od nqx[0:1] qx[0:1] nqx[0:1] qx[0:1]
idt8T79S838-08NLGI revision a january 29, 2014 11 ?2014 integrated device technology, inc. idt8t79s838-08i data sheet 1-to-8 differential to universal output fanout buffer parameter measurement in formation, continued offset voltage setup differential output voltage setup applications information recommendations for unused input and output pins i nputs: lvcmos control pins all control pins have internal pulldowns; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: lvpecl outputs any unused lvpecl output pairs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should ei ther be left floating or terminated. lvds outputs all unused lvds output pairs can be either left floating or terminated with 100 ? across. if they are left floating, there should be no trace attached. lvcmos outputs the unused lvcmos output can be left floating. there should be no trace attached. o u t o u t lv d s dc inp u t ? v o s / ? v o s v cc 100 o u t o u t dc inp u t v cc lv d s
idt8T79S838-08NLGI revision a january 29, 2014 12 ?2014 integrated device technology, inc. idt8t79s838-08i data sheet 1-to-8 differential to universal output fanout buffer wiring the differential input to accept single-ended levels figure 2 shows how a differential input can be wired to accept single ended levels. the reference voltage v 1 = v cc /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should be located as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v 1 in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v cc = 3.3v, r1 and r2 value should be adjusted to set v 1 at 1.25v. the values below are for when both the single ended swing and v cc are at the same voltage. this configuration requires that th e sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the input will at - tenuate the signal in half. this can be done in one of two ways. first, r3 and r 4 in parallel should equal the transmission line impedance. for most 50 ? applications, r3 and r4 can be 100 ? . the values of the resistors can be increased to reduce the loading for slower and weaker lvcmos driver. when using single-ended signaling, the noise rejection benefits of differ ential signaling are reduced. even though the differential input can ha ndle full rail lvcmos signaling, it is recommended that the amplitu de be reduced. the datasheet spec - ifies a lower differential amplitude, however this only applies to differ - ential signals. for single-ended applications, the swing can be larger, ho w ever v il cannot be less than -0.3v and v ih cannot be more than v cc + 0.3v. though some of the recommended components might not be used, the pads should be placed in the layout. they can be uti - lized for debugging purposes. the dat asheet specific atio ns are char - acterized and guaranteed by using a differential signal. rec eiv er + - r4 10 0 r3 10 0 rs zo = 50 ohm ro driv er vcc vcc r21k r11k c1 0.1uf ro + rs = zo v1 vc c vc c figure 2. recommended schematic for wiring a diff erential input to accept single-ended levels
idt8T79S838-08NLGI revision a january 29, 2014 13 ?2014 integrated device technology, inc. idt8t79s838-08i data sheet 1-to-8 differential to universal output fanout buffer 3.3v lvpecl clock input interface the pclk /npclk accepts lvpecl, lvds and other differential sig- nals. both v swing and v oh must meet the v pp and v cmr input re- quirements. figures 3a to 3c show interface examples for the pclk/ npclk input driven by the most common driver types. the input in- terfaces suggested here are examples only. if the driver is from an- other vendor, use their terminatio n recommendation. please consult with the vendor of the driver com ponent to confirm the driver termi- nation requirements. figure 3a. pclk/npclk input driven by a ? 3.3v lvpecl driver figure 3c. pclk/npclk input driven by a ? 3.3v lvds driver figure 3b. pclk/npclk input driven by a ? 3.3v lvpecl driver with ac couple r3125 r4125 r184 r284 3.3v zo = 50 zo = 50 pclknpclk 3.3v 3.3v lvpecl lvpeclinput 3.3v r1100 ? lvd s pclknp clk 3.3v lvpe cl input zo = 50 ? zo = 50 ?
idt8T79S838-08NLGI revision a january 29, 2014 14 ?2014 integrated device technology, inc. idt8t79s838-08i data sheet 1-to-8 differential to universal output fanout buffer 2.5v lvpecl clock input interface the pclk /npclk accepts lvpecl, lvds and other differential sig- nals. both v swing and v oh must meet the v pp and v cmr input re- quirements. figures 4a to 4c show interface examples for the pclk/ npclk input driven by the most common driver types. the input in- terfaces suggested here are examples only. if the driver is from an- other vendor, use their terminatio n recommendation. please consult with the vendor of the driver com ponent to confirm the driver termi- nation requirements. figure 4a. pclk/npclk input driven by a ? 2.5v lvpecl driver figure 4c. pclk/npclk input driven by a ? 2.5v lvds driver figure 4b. pclk/npclk input driven by a ? 2.5v lvpecl driver with ac couple 2. 5v p c l k np c l k 2. 5v 2. 5v lvpe cl lvpe c l in p u t p c l k np c l k
idt8T79S838-08NLGI revision a january 29, 2014 15 ?2014 integrated device technology, inc. idt8t79s838-08i data sheet 1-to-8 differential to universal output fanout buffer lvds driver termination for a general lvds interface, the recommended value for the termination impedance (z t ) is between 90 ? and 132 ? . the actual value should be selected to match the differential impedance (z 0 ) of your transmission line. a typical point-to-point lvds design uses a 100 ? parallel resistor at the receiver and a 100 ? differential transmission-line environment. in order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. idt offers a full line of lvds compliant devices with two types of output structures: current source and voltage source. the standard termination schematic as shown in figure 5a can be used with either type of output structure. figure 5b , which can also be used with both output types, is an optional termination with center tap capacitance to help filter comm on mode noise. the capacitor value should be approximately 50pf. if using a non-standard termination, it is recommended to contact idt and confirm if the out put structure is current source or voltage source type. in addition, since these outputs are lvds compatible, the input receiver?s amplitude and common-mode input range should be verified for compatibility with the output. lvds ? driver lvds ? driver lv d s ? receiver lv d s ? receiver z t c z o ? z t z o ? z t z t 2 z t 2 figure 5a. standard termination figure 5b. optional termination lvds termination
idt8T79S838-08NLGI revision a january 29, 2014 16 ?2014 integrated device technology, inc. idt8t79s838-08i data sheet 1-to-8 differential to universal output fanout buffer termination for 3.3v lvpecl outputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recom - mended only as guidelines. the differential outputs are low im pedance follower outputs that gen- erate ecl/lvpecl compatible outputs. therefore, terminating resis- tors (dc current path to ground) or current sources must be used for functionality. these output s are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 6a and 6b show two different layouts which are recommended only as guide- lines. other suitable clock layouts may exist and it would be recom- mended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. figure 6a. 3.3v lvpecl output termination figure 6b. 3.3v lvpecl output termination r184 ? r284 ? 3.3v r3125 ? r4125 ? z o = 50 ? z o = 50 ? lvpecl input 3.3v 3.3v +_
idt8T79S838-08NLGI revision a january 29, 2014 17 ?2014 integrated device technology, inc. idt8t79s838-08i data sheet 1-to-8 differential to universal output fanout buffer termination for 2.5v lvpecl outputs figure 7a and figure 7b show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to terminating 50 ? to v cc ? 2v. for v cc = 2.5v, the v cc ? 2v is very close to ground level. the r3 in figure 7b can be eliminated and the termination is shown in figure 7c. figure 7a. 2.5v lvpecl driver termination example figure 7c. 2.5v lvpecl driver termination example figure 7b. 2.5v lvpecl driver termination example 2.5v lvpecl driver v cc = 2.5v 2.5v 2.5v 50 50 r1250 r3250 r262.5 r462.5 + ? 2.5v lvpecl driver v cc = 2.5v 2.5v 50 50 r150 r250 + ? 2.5v lvpecl driver v cc = 2.5v 2.5v 50 50 r150 r250 r318 + ?
idt8T79S838-08NLGI revision a january 29, 2014 18 ?2014 integrated device technology, inc. idt8t79s838-08i data sheet 1-to-8 differential to universal output fanout buffer vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 8. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the ther - mal/electrical performance. sufficient clearance should be designed on the pcb be tween the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a sol - der joint, thermal vias are necessary to eff ectively conduct from the surface of the pcb to the ground plane(s). the land pattern must be connected to ground through these vias. the vias act as ?heat pipes?. the number of vias (i.e. ?heat pipes?) are application specific and de - pendent upon the package power dissipation as well as electrical cond uctivity requirements. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recom - mended to use as many vias connected to ground as possible. it is al so recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barre l plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, please refer to the application note on the surface mount assembly of amkor?s thermally/ electrically enhance leadframe base package, amkor technology. figure 8. p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale) solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
idt8T79S838-08NLGI revision a january 29, 2014 19 ?2014 integrated device technology, inc. idt8t79s838-08i data sheet 1-to-8 differential to universal output fanout buffer 3.3v lvds power considerations this section provides information on power dissipation and junc tion temperature for the idt8t79s 838-08i. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the idt8t79s838-08i is the sum of the core power plus the power dissipated due to the load. ? the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. ? power (core) max = v cc_max * i cc_max = 3.465v * 235ma = 814.3mw 2. junction temperature. junction temperature, tj, is the temperatur e at the junction of the bond wire and bo nd pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 48.9c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.814w * 48.9c/w = 124.8c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 6. thermal resistance ? ja for 32-lead vfqfn package ? ja by velocity meters per second 012 multi-layer pcb, jedec standard te st boards 48.9c/w 42c/w 39.4c/w
idt8T79S838-08NLGI revision a january 29, 2014 20 ?2014 integrated device technology, inc. idt8t79s838-08i data sheet 1-to-8 differential to universal output fanout buffer 3.3v lvpecl power considerations this section provides information on power dissipation and juncti on temperature for the idt8t79s 838-08i, for all outputs that a re configured to lvpecl. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the idt8t79s838-08i is the su m of the core power plus the power dissipated due to loading. ? the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated due to loading. ? power (core) max = v cc_max * i ee_max = 3.465v * 135ma = 467.8mw ? power (outputs) max = 31.55mw/loaded output pair ? if all outputs are loaded, the total power is 8 * 31.55mw = 252.4mw total power_ max (3.465v, with all outputs s witching) = 467.8mw + 252.4mw = 720.2mw 2. junction temperature. junction temperature, tj, is the temperatur e at the junction of the bond wire and bo nd pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the a ppropriate junction-to-ambient thermal resistance ? ja must be used. assuming no airflow and a multi-layer board, the appropriate value is 48.9c/w per table 7 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.720w * 48.9c/w = 120.2c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depe nding on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 7. thermal resistance ? ja for 32-lead vfqfn package ? ja by velocity meters per second 012 multi-layer pcb, jedec standard te st boards 48.9c/w 42c/w 39.4c/w
idt8T79S838-08NLGI revision a january 29, 2014 21 ?2014 integrated device technology, inc. idt8t79s838-08i data sheet 1-to-8 differential to universal output fanout buffer 3. calculations and equations. the purpose of this section is to calculate the power dissipation fo r the lvpecl output pairs. lvpecl output driver circuit and termination are shown in figure 9. v out v cc v cc - 2v q1 rl figure 9. lvpecl driver circuit and termination t o calculate power dissipation per output pair due to loading, use the following equations which assume a 50 ? load, and a termination voltage of v cc ? 2v. ? for logic high, v out = v oh_max = v cc_max ? 0.75v ? (v cc_max ? v oh_max ) = 0.75v ? for logic low, v out = v ol_max = v cc_max ? 1.6v ? (v cc_max ? v ol_max ) = 1.6v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cc_max ? 2v))/r l ] * (v cc_max ? v oh_max ) = [(2v ? (v cc_max ? v oh_max ))/r l ] * (v cc_max ? v oh_max ) = ? [(2v ? 0.75v)/50 ? ] * 0.75v = 18.7 5mw pd_l = [(v ol_max ? (v cc_max ? 2v))/r l ] * (v cc_max ? v ol_max ) = [(2v ? (v cc_max ? v ol_max ))/r l ] * (v cc_max ? v ol_max ) = ? [(2v ? 1.6v)/50 ? ] * 1.6v = 12.80mw total power dissipation per output pair = pd_h + pd_l = 31.55mw
idt8T79S838-08NLGI revision a january 29, 2014 22 ?2014 integrated device technology, inc. idt8t79s838-08i data sheet 1-to-8 differential to universal output fanout buffer reliability information table 8. ? ja vs. air flow table for a 32-lead vfqfn package transistor count the transistor count for idt8t79s838-08i is: 2618 ? ja vs. air flow meters per second 012 multi-layer pcb, jedec standard te st boards 48.9c/w 42.0c/w 39.4c/w
idt8T79S838-08NLGI revision a january 29, 2014 23 ?2014 integrated device technology, inc. idt8t79s838-08i data sheet 1-to-8 differential to universal output fanout buffer 32 lead vfqfn package out line and package dimensions
idt8T79S838-08NLGI revision a january 29, 2014 24 ?2014 integrated device technology, inc. idt8t79s838-08i data sheet 1-to-8 differential to universal output fanout buffer ordering information table 9. ordering information part/order number marking package shipping packaging temperature 8T79S838-08NLGI idt8T79S838-08NLGI ?lead-free? 32 lead vfqfn tray -40 ? c to 85 ? c 8T79S838-08NLGI8 idt8T79S838-08NLGI ?lead-free? 32 lead vfqfn tape & reel -40 ? c to 85 ? c
idt8t79s838-08i data sheet 1-to-8 differential to universal output fanout buffer disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the ri ght to modify the products and/or specif ications described herein at any time and at idt s sole discretion. all information in this document, including descriptions of product features and performance, is s ubject to change without notice. performance specifications and the operating parameters of the described products ar e determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idts products for any partic ular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a gui de and does not convey any license under intellectual property rights of idt or any third parties. idts products are not intended for use in applications involving extreme environmenta l conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to signifi- cantly affect the health or safety of users. anyone using an id t product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered tr ademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2014. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 weve got your timing solution

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